1. Field of the Invention
This invention relates to a semiconductor device having reliable multi-layered wiring and a method of manufacturing the semiconductor device.
2. Description of the Related Art
Recently, LSIs have been highly integrated, and multi-layered wiring has been generally formed on a semiconductor substrate.
A method for manufacturing a conventional semiconductor device will be explained.
First, a first wiring layer made of an Al alloy is formed on a semiconductor substrate, and then an interlayer insulating layer is deposited on the first wiring layer. Subsequently, the interlayer insulating layer is flattened by the use of the etching-back method so as to prevent short-circuiting between wiring layers. A contact hole is formed in the interlayer insulating layer, and a second wiring layer made of an Al alloy is formed on the inner surface of the opening and on the interlayer insulating layer such that the second wiring layer is electrically connected to the first wiring layer.
In this conventional method, the higher the temperature during depositing the interlayer insulating layer, the lesser the concentration of an impurity (e.g. H.sub.2 O ) contained in the layers. However, if the interlayer insulating layer is formed at a temperature higher than 350.degree. C., hillocks will grow from the first wiring layer made of an Al alloy. Such hillocks more and more grow in a flattening process performed later, which may result in short-circuiting between the first and second wiring layers. To prevent the growth of the hillocks, there is a case where a SiO.sub.2 layer with a thickness of about 2000 .ANG. is formed on the first wiring layer at low temperature, and then a thick interlayer insulating layer is formed on the SiO.sub.2 layer at high temperature so as to obtain a predetermined breakdown voltage. Since in this case, the SiO.sub.2 layer formed at low temperature has low quality, a gas, such as H.sub.2 O gas, is discharged from the SiO.sub.2 layer after the contact hole is formed in the SiO.sub.2 layer and the interlayer insulating layer to connect the first and second wiring layers to each other. The discharged gas inevitably degrades the reliability of contact between the first and second wiring layers.
Further, it is considered as another method for preventing the growth of the hillocks, to employ a liquid phase method using H.sub.2 SiF.sub.6, in which an interlayer insulating layer made of SiO.sub.2 is formed on the first wiring layer. In this case, however, if the first wiring layer made of an Al alloy is directly coated with H.sub.2 SiF.sub.6, then the layer will be solved. Therefore, it is necessary to form an interlayer insulating layer with the use of the liquid phase method, after depositing a SiO.sub.2 layer with a thickness of 1000-2000 .ANG. on the first wiring layer by the CVD method. Thus, a large number of steps is required, and a large amount of dust will be generated during the steps.
In addition, in the interlayer-flattening step performed by the etching-back method, it is difficult to control the thickness of an etched portion of the interlayer insulating layer, and the first wiring layer may be exposed as a result of over-etching. At this time, hillocks grow from the first wiring layer, resulting in short-circuiting between the wiring layers. Therefore, the interlayer insulating layer cannot be completely flattened. Moreover, it is very difficult to form third and fourth wiring layers, and hence to produce an LSI with the third and fourth wiring layers.